The disclosed embodiments of the present invention relate to a time-to-digital converter (TDC) which may be part of an all-digital phase-locked loop, and more particularly, to a method of estimating/calibrating the TDC mismatch and a related apparatus.
All-digital phase-locked loop (ADPLL) is a very attractive technique for a multi-radio system on chip (SOC). It results in the smaller occupied circuit area and lower power consumption, especially compared with the analog PLL circuit. For example, an ADPLL includes a digitally-controlled oscillator (DCO), a time-to-digital converter (TDC), and a digital loop filter. The TDC is an important circuit module used to measure timestamp, and the measurement result is a finite-length digital word. The TDC used in the ADPLL acts as a phase/frequency detector and a charge pump used in the analog PLL. Taking the advantage of the digital implementation, the TDC is easily to be programmed and calibrated, which makes it very suitable for the ADPLL. Recently, due to development of the deep-submicron CMOS technology, the TDC may be implemented utilizing a simple inverter chain, with each inverter providing a stable delay. As the TDC is a key component of the ADPLL, the gain and linearity performance of the TDC significantly affects the quality of the ADPLL. There is a need for an innovative design which can calibrate the TDC gain and nonlinearity precisely without adding too many extra detection and compensation circuits.